This page is set up to show what happens when we depress the ON button to start our computer.

    The below image shows a few Power Supply lines in states reflecting the PSU in an Off condition. The 5.0 Volt Standby voltage is held at a Logic High as a result of an internal "pull up" resistor located in the PSU. Currently this voltage is about 5.078 Volts in the example. When the power button is depressed this 5.0 Volts should transition to a logic low level. This is accomplished by a series of circuits that are part of the computer's motherboard. In addition to going low when the front panel button is depressed, this line can also go low for various "Wake On" features such as wake on LAN. If we look at the main PSU to motherboard connector this line is Pin #14 on a 20 pin motherboard connector and pin #16 on a 24 pin motherboard connector. This line is generally the only Green colored wire in the main PSU connector. This holds true for just about all ATX Form Factor PSUs. There are exceptions such as high end server PSUs that use different color schemes. The lower portion of the graph reflects the PWR_OK line and is pin #8 on either a 20 or 24 pin main motherboard connector. The wire color for this line is Gray in color.



    The below image shows what happens the instant the front panel power button is depressed. I have placed a vertical cursor at this point in time. Note that at this point in time the record process is at 13.0365 seconds into the recording stage. We clearly see the 5.0 Volt level of the PWR_ON transition towards 0 Volts or for our purposes a logic low status. This TTL (Transistor Transistor Logic) is what turns the PSU on. We can also see at this point in time the logic level of the lower trace PWR_OK is still at a logic low state at about .015 Volt or 15 milli-volts. The instant the PSU starts it immediately begins looking at its output rails. Once the 3.3, 5.0 and 12.0 rails are exceeding their minimum acceptable tolerance the PSU will send out a PWR_OK signal. At this point the PWR_OK line will transition to a logic high state.  



    This next image shows where the PWR_OK transitions to a logic high telling the system CPU that the PSU voltages are within tolerance for normal operation. I have placed the vertical cursor over the point where the transition occurs. Note here the timeline is at 13.4400 seconds. What is of concern here is if the PSU sends the PWR_OK signal within an allotted time period assuming things are OK. We can call the PWR_ON Time0 and the PWR_OK Time1. If we subtract T0 from T1 we will get the time from PWR_ON to PWR_OK. Thus we have 13.4400 - 13.0365 = 0.4035 Seconds or 403.5 milliseconds. Just over .4 second was the time it took from depressing the front panel power button to a PWR_OK signal to be sent to the motherboard CPU.

    The following information is taken from the PSU design guide version 2.01:

3.3.2. PS_ON#

PS_ON# is an active-low, TTL-compatible signal that allows a motherboard to remotely

control the power supply in conjunction with features such as soft on/off, Wake on LAN*,

or wake-on-modem. When PS_ON# is pulled to TTL low, the power supply should turn

on the four main DC output rails: +12VDC, +5VDC, +3.3VDC and -12VDC. When

PS_ON# is pulled to TTL high or open-circuited, the DC output rails should not deliver

current and should be held at zero potential with respect to ground. PS_ON# has no effect

on the +5VSB output, which is always enabled whenever the AC power is present. Table

14 lists PS_ON# signal characteristics.

The power supply shall provide an internal pull-up to TTL high. The power supply shall

also provide de-bounce circuitry on PS_ON# to prevent it from oscillating on/off at startup

when activated by a mechanical switch. The DC output enable circuitry must be SELVcompliant.

The power supply shall not latch into a shutdown state when PS_ON# is driven active by

pulses between 10ms to 100ms during the decay of the power rails.

Table 14. PS_ON# Signal Characteristics

Min. Max.

VIL, Input Low Voltage 0.0 V 0.8 V

IIL, Input Low Current (Vin = 0.4 V) -1.6 mA

VIH, Input High Voltage (Iin = -200 μA) 2.0 V

VIH open circuit, Iin = 0 5.25 V


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3.3.1. PWR_OK

PWR_OK is a “power good” signal. It should be asserted high by the power supply to

indicate that the +12 VDC, +5VDC, and +3.3VDC outputs are above the under-voltage

thresholds listed in Section 3.2.1 and that sufficient mains energy is stored by the converter

to guarantee continuous power operation within specification for at least the duration

specified in Section 3.2.11, “Voltage Hold-up Time.” Conversely, PWR_OK should be deasserted

to a low state when any of the +12 VDC, +5 VDC, or +3.3 VDC output voltages

falls below its under-voltage threshold, or when mains power has been removed for a time

sufficiently long such that power supply operation cannot be guaranteed beyond the powerdown

warning time. The electrical and timing characteristics of the PWR_OK signal are

given in Table 13 and in Figure 6.

Table 13. PWR_OK Signal Characteristics

Signal Type +5 V TTL compatible

Logic level low < 0.4 V while sinking 4 mA

Logic level high Between 2.4 V and 5 V output while sourcing 200 μA

High-state output impedance 1 kΩ from output to common

PWR_OK delay 100 ms < T3 < 500 ms

PWR_OK risetime T4 10 ms

AC loss to PWR_OK hold-up time T5 16 ms

Power-down warning T6 1 ms

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    The power supply used in these test was an Antec True Power 2.0 550 Watt PSU. The signals were tapped off the main motherboard PSU connector. The computer was my own everyday machine with nothing special. We only looked at a very small portion of the logic and timing of a PSU startup. Any good and reputable PSU should perform to the same specifications. However, it should be noted there is a common trick used on substandard, cheap power supplies. Frequently a cheap PSU will tie the PWR_OK line to the 5.0 Volt rail. These units should be avoided. They are junk!

    In the event the CPU does not see a PWR_OK signal the PWR_ON line will return to a logic high and the sytstem will shutdown.